A common practice in fabricating Electrically Erasable Programmable Read Only Memory (EEPROM) was to produce N-channel cells over a P-well substrate because of a simpler manufacturing process and lower programming voltages. The approach used by Caywood; as disclosed in U.S. Pat. No. 5,986,931, entitled “Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory” which is a continuation-in-part of U.S. Pat. Nos. 5,790,455, and 5,986,931 (Caywood 2) and U.S. Pat. No. 5,790,455 (Caywood 1), incorporated by reference herein for all purposes; produces precisely the opposite configuration, i.e., P-channel devices over an N-well, which itself resides in a P-type substrate. The novelty of the Caywood approach is the reduction in magnitude of the applied voltage required for erasing and writing to the device while maintaining a similar writing speed as found in the related technology prior to Caywood as well as the elimination of certain components functionally necessary in the related technology.
Referring to FIG. 1, the N-channel memory device related technology is illustrated. Each memory transistor (MEM) required a row select transistor (SEL), which controlled the data received from the bit lines (BL). Also, if byte addressing was desired, then the device included a byte select transistor (BYTE) for every eight memory transistors. The problem solved by Caywood with the advent of a P-channel/N-well device was the elimination of the row select transistors. Even after Caywood, byte selection still required the presence of the byte select transistors. The elimination of the byte select transistors resulted in the undesirable effect that the entire row must be reprogrammed following an erase operation.
Referring to FIG. 2, the Caywood approach is illustrated in general terms for a single memory transistor 1. The N-well 3 is created within a P-type substrate 2. The P-channel for the drain 4 and source 5 is created within the N-well 3. Poly 1 or the floating gate 6 of the memory transistor 1 is created after the active region for the drain 4 and source 5. Poly 2 or the control electrode 7 of the memory transistor is fabricated over the floating gate. Various non-conductive layers 8 insulate the P-channel 4 and 5, the floating gate 6 and the control electrode 7 from each other.
FIG. 3 illustrates a plurality of cell rows 100, typically connected to gate electrodes of memory transistors and a plurality of columns 200 typically connected to source and drain electrodes of memory transistors in the array, with both cell rows and cell columns existing on a single N-well 300 substrate. The limitation to the Caywood P-channel memory arrays, as shown in FIG. 3, is that all memory cells in any particular row must be selected, thus written or erased, during a particular operation.
Alternatively stated, as disclosed by Caywood, the cell rows are not segmented such that some memory cells in the cell row may be selected for writing while other memory cells in the row are not. Thus, in order to program the contents of a single memory cell, the entire cell row must then be programmed in order to change the data in one memory cell.
In many applications it is desired to change the data in the memory array, one byte at a time. In the N-channel device prior art, this feature was accomplished by the inclusion of a byte select transistor (BYTE) for each eight memory transistors as shown in FIG. 1. The disadvantage of this approach is the increased demand for silicon area to accommodate the overhead of the byte select transistor (BYTE). For example, from solely a transistor perspective, a byte select transistor (BYTE) for every eight memory transistors requires an 11 percent overhead (i.e., 1/9).
Moreover, the capability of changing one byte at a time would give an endurance advantage over row select memory arrays because only one byte of cells would need to undergo the electrical stress of the programming cycle as opposed to the entire row. It is well known to those skilled in the art of semiconductor memory fabrication that one cause of EEPROM failure is attributable to excessive erase/write operations.
As the memory cell and supporting circuitry transistor circuits are fabricated with smaller geometries, voltage breakdown becomes more of a problem. Since the erase and write operations require relatively high voltages in comparison to read operations, the smaller geometry circuit elements are more voltage stressed than were older technology memory cells and supporting circuitry that used larger geometry transistors.